Planar Transistor Network Visualization Algorithm
نویسندگان
چکیده
The visualization of switch networks is a very interesting tool for analysis and verification of logic cells generated automatically. In this context, the use of graph theory is very useful to attain this objective. The proposed algorithm satisfies this necessity to represent complementary series/parallel and partially “bridge” network logic styles, avoiding any wire crossing. A tool prototype is available.
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تاریخ انتشار 2009